TPIC6A596NE

TPIC6A596NE contains an 8-bit serial input and parallel output shift register, which supplies power to the 8-bit D-type storage register. Data is transmitted through the shift register and the storage register on the rising edges of the shift register clock and the register clock respectively. When the shift register clear (SRCLR)\ is high, the storage register transfers data to the output buffer. The serial output is output to the device on the falling edge of SRCK to provide additional hold time for cascaded applications.