CD74HC4094PWR

CD74HC4094PW is an 8-bit serial input/serial or parallel output shift memory bus register with memory register and three-state output. Both the shift register and the storage register have independent clocks. The data is shifted when the CP input transitions from low to high. Data is provided on QS1 where the CP input transitions from low to high to allow cascading when the clock edge is fast. At the next high-to-low transition of the CP input, QS2 provides the same data to allow cascading when the clock edge is slow. When the STR input is high, the data in the shift register is transferred to the storage register. As long as OE is high, the data in the storage register will appear on the output.