CD74HCT165E

CD74HCT165E, HCT series, 74HCT165, parallel to serial, 1 element, 8 bits, DIP, 16 pins

When PL\ is high, the data enters the register serially at the DS input and moves one bit to the right with each forward clock transition. This function allows the parallel-to-serial converter to be expanded by inputting the Q7 output to the DS input of the subsequent device. For predictable operations, the transition of CE\ from low to high should only occur when CP is high. In addition, CP and CE\ should be low before PL transitions from low to high to prevent shifting data when PL\ changes to high.